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We propose a technology to reduce the specific on-resistance (Ron,sp) of 1.7 kV voltage rating VDMOSFET on 4H-SiC, including channel area process optimization, channel and source self-alignment, recessed source contact, etc. The technology improves the Baliga’s figure-of-merit (BFOM), which is superior to existing products and published literature with the same voltage rating, and has the advantage of continuously reducing the cell pitch.
Future Tech | Electronics ＆ Optoelectronics/Green Energy ＆ EnvironmentIn this project, power-efficient architectures for the PAM-4 transmitter and receiver are developed in 28nm CMOS. It demonstrates a 112Gb/s PAM-4 end-to-end link under 10dB channel loss with 2.5pJ/b power efficiency. The XSR transceiver can be utilized as a chiplet and applied into heterogeneous integration for next-generation advanced package applications.
Future Tech | Materials ＆ Chemical Engineering ＆ Nanotech/Electronics ＆ OptoelectronicsThis technology is divided into three parts: making the sample into a need le shape with a focused ion beam, collecting atomic-level projection imag es of the sample at various angles with a spherical aberration-corrected el ectron microscope, and iteratively optimizing the three-dimensional tomo graphic reconstruction with Fourier transform. In this way, the three-dime nsional atomic structure can be obtained in a FinFET sample with a resolut ion of 1.8 angstroms. First, the target is to prepare the test piece into a needle-shaped sample w ith a diameter of less than 50 nanometers. When preparing, we first positi on the sample and use high-voltage ion beam current to roughly cut it int o a needle shape with a diameter of about 5 microns. Then, the ion beam current is reduced to 300 pA, and the cutting is carried out using a ring m ask. Finally, the voltage of the ion beam is reduced to 5 kV, and the current is reduced to below 100 pA so that the damage caused by the ion beam is minimized, reaching a needle with a diameter of 50 nanometers. Then, use a scanning transmission electron microscope (STEM) with a sph erical aberration corrector and an annular dark field detector (ADF) to coll ect atomic projections of the needle-shaped sample at all angles. STEM-A DF images are dark field images, also known as Z-contrast images, and do not have the problem of contrast reversal caused by changing the focus. T herefore, the SiGe thin film, high dielectric constant thin film, ferroelectric layer, and metal gate are promising for observation. Finally, 3D images were obtained using optimized tomographic reconstru ction techniques. Since the experimental data are on the polar grid points, and the reconstruction is on the Cartesian grid points, using all the experi mental data to perform global interpolation in the Fourier space and then performing inverse Fourier transform will obtain the 3D reconstruction wi th a better resolution.
Future Tech | Electronics ＆ OptoelectronicsThis technology applies high-voltage wide-bandgap components to the converters used in electric vehicle charging. Due to the high-voltage tolerance and rapid switching characteristics of these components, the technology enables fast charging capabilities for electric vehicles, while also improving system conversion efficiency and power density.
Future Tech | Materials ＆ Chemical Engineering ＆ Nanotech/Electronics ＆ OptoelectronicsAtom probe tomography (APT) is a novel characterization technique capable of resolving the three-dimensional atomic distribution in materials or devices, achieving sub-nanometer spatial resolution and nearly 20 ppm compositional detection limit. This unique combined analytical capability sets it apart from transmission electron microscopy (TEM), which is limited by compositional limit, and secondary ion mass spectrometry, which is limited by spatial resolution. Hence, it has become a crucial characterization technique for contemporary research and development in miniaturized, heterogeneous, and three-dimensional semiconductor devices.
Future Tech | Materials ＆ Chemical Engineering ＆ Nanotech/Electronics ＆ OptoelectronicsThe Pericardium/Aorta Segmentation and Cardiovascular Risk Prediction AI Total Solution Model, HeaortaNet, is a deep learning model based on UNet and attention gate, and had been trained by >70,000 axial images from 200 patients with verified annotations of the pericardium and aorta. It shortens the time for data processing from 60 minutes, by manual segmentation of both pericardium and aorta, to 0.4 seconds. The segmentation accuracy is 94.8% for the pericardium, and 91.6% for the aorta.
Future Tech | Biotechnology ＆ Medical care/Machinery ＆ SystemExtreme ultraviolet (EUV) lithography is a process using EUV light to transf er a mask pattern onto a wafer. At present, semiconductor manufacturers such as TSMC have successfully employed 13.5 nm light for photolithogra phy, reaching a 3 nm mass production process. In advanced wafer manufa cturing, real-time monitoring of the EUV beam quality is essential as it pro vides important guidance for laser adjustment and/or contaminant remov al. Current EUV detectors on the market are expensive (more than one millio n NT dollars), short-lived, and bulky. To solve this issue, we have develope d an EUV imaging device that is low cost, small size, and easy to operate. S pecifically, we use fluorescent nanodiamonds (FNDs for short) as the EUV scintillators. FNDs are produced by electron bombardment of diamond po wers containing ~100 ppm nitrogen atoms to create carbon vacancies, foll owed by vacuum annealing to form stable nitrogen-vacancy color centers. Composed of mainly carbon elements, FNDs are non-toxic and environme ntally friendly. In addition, FNDs are robust and can form stable thin films by electrospray deposition. These films are non-hygroscopic and can with stand high temperature and high energy photon irradiation, exhibiting ex cellent durability. We have successfully used the light sources at the National Synchrotron R adiation Research Center to prove the principle. It is demonstrated that F NDs can absorb VUV (vacuum ultraviolet), EUV, and X-ray light effectively, and convert them efficiently into orange-red light (550–800 nm). A lens sy stem collects the fluorescence and focuses it on a detector such as CMOS and CCD, enabling the detection of EUV using existing technologies and a chieving a spatial resolution of 30 μm. This invention has received patents from Taiwan and the United States in 2 021. Related research results have been published on Angew. Chem. Int. E d. 56, 14469 (2017) and ACS Appl. Mater. Interfaces 12, 3847 (2020).
Future Tech | Electronics ＆ OptoelectronicsWe exploit deep learning techniques to develop EDA tools for semiconductor manufacturing. Our EDA tools can predict circuit shape distortions caused by the lithography processes and thus assess the photomask correction results at an early stage. These tools can be applied to layout's OPC simulation, layout hotspot detection, IC defect detection, and photomask optimization.
Future Tech | Materials ＆ Chemical Engineering ＆ NanotechElectrochemical etching and the process of applying related principles are important semiconductor material technologies, and are now also the key technologies for fabricating nanostructures in nanotechnology. The key s ubstance for the electrochemical etching chemical reaction is the hole (h +), because the hole can enter the chemical bond connecting the solid sur face atoms and weaken bond strength to result in etching. Since the N-type silicon substrate lacks the element of anodic oxidation - holes, this becomes the biggest obstacle in making the porous layer. The e xisting method is to irradiate the surface or the back of the silicon substrat e with strong light from a halogen lamp to generate holes to assist the etc hing during etching. However, the hole density excited by projected light i s easily affected by the intensity of the light source, distance, medium, wa velength, etc., and is far less stable than anodic oxidation in a dark room. This technology uses hydrophobic wafer bonding technology to bond P-t ype silicon as an intermediary electrode on the back of N-type silicon to f orm a detachable PN junction and then connect electrodes to form N-typ e Si/P-type Si/ Electrode sandwich structure. The P-type silicon and N-typ e silicon form a PN junction, which can convert the holes in the N-type sili con from "secondary carrier flow" to "main control current", thus greatly i mproving the anodic oxidation efficiency of the substrate surface . After t he electrochemical etching process is completed, the P-type silicon used a s the intermediary electrode can be easily separated from the N-type silic on, so that the processed N-type silicon remains pure and free from pollut ion. This technology has been successfully expanded from the application of N-type silicon crystal materials to N-type silicon carbide materials. It is expected to be extended and applied to other N-type semiconductor mat erials.
Future Tech | Electronics ＆ OptoelectronicsThe epitaxial layer structure of the GaN-on-Si substrate was improved, and the HEMT device fabrication process was optimized to achieve a GaN HEMT device with a breakdown voltage of >1200V
Future Tech | Materials ＆ Chemical Engineering ＆ NanotechDue to the electric field crowding caused by the curvature at the edge of P-N junction, the edge of power devices is usually the location of priority breakdown, so it is necessary to design an edge termination protection structure. Using a multiple floating zone junction termination extension (MFZ JTE) structure and optimizing parameters such as concentration, depth, and spacing, the width of the termination structure is only 30% of the products of the same 1.7 kV voltage rating. We also propose a double-layer structure and local oxidation of SiC (LOCOSiC) technologies to improve the immunity of charges in field oxide. Our edge termination structure has great application advantages.
Future Tech | Electronics ＆ Optoelectronics/Green Energy ＆ EnvironmentIntroducing a groundbreaking high-density 3D Via Resistive Random Access Memory (RRAM) architecture seamlessly compatible with Fin Field-Effect Transistors (FinFETs) in logic processes. Through the careful design of a structure where vias and metal wires remain intentionally isolated in the layout, a Via RRAM is ingeniously crafted. This approach offers exceptional stackability, permitting each metal wire layer within the memory unit to incorporate a pair of RRAM elements, culminating in the creation of a remarkably high-density stackable embedded memory solution.
Future Tech | Materials ＆ Chemical Engineering ＆ NanotechIn the technology, we integrate Taiwan’s strength in high-brightness LED and our strength in high-power sources to commercialize LED-pumped so lid-state laser. This product is the first commercial-grade LED-pumped soli d-state laser in the world, all made in Taiwan! In our product, the LED generates high-power pump light to achieve popu lation inversion in a laser gain crystal installed in a laser cavity. There are a few challenges in developing such a unique laser source, including the lar ge divergence of the LED light and the high heat generated in the laser m odule. To overcome these problems, we first invent a pump-light structure that can efficiently collect the LED light to the laser-gain crystal. Secondly, we design an efficient cooling structure to remove the waste heat from th e laser as well as the LED dies. Our LED-pumped laser has generated more than 500-mJ pulse energy repeating at 10 Hz at 1064 nm in quasi-CW ope ration. By inserting a laser Q-switch in the laser cavity, the peak laser powe r reaches nearly 3 MW in a ~25-ns pulse width. This is the most powerful a nd the only industry-grade LED-pumped sold-state laser in the world.
Future Tech | Electronics ＆ OptoelectronicsHighly stacked channels with extremely high-k gate stacks: Our team has successfully integrated the extremely high-k Hf0.2Zr0.8O2 g ate stacks (k=47) into both the 8 stacked Ge0.95Si0.05 nanowires and nan osheets. The nanowires and nanosheets achieve the record ION per footpr int of 9200μA/μm and the record ION per stack of 360μA at VOV=VDS=0. 5V, respectively, among all Si/GeSi/Ge 3D nFETs. The simulation of vs [Zr] i n HZO confirms that the k can be peaked at [Zr]=80%. The significant gate delay improvement by combining the extremely high-k gate stacks and th e large floor number is confirmed by simulation. Stacked GeSi GAA Nanosheet FeFETs: FeFETs are promising candidates for embedded non-volatile memory due to the CMOS-compatible process for scalability, simple 1T architecture, lo w write energy, and nondestructive read. A large memory window (MW) is required for FeFET operations, particularly for multi bits. Our team has suc cessfully developed the world first stacked GeSi nanosheet gate-all-aroun d (GAA) FeFETs, featuring large memory window of 1.8V at the low write v oltage of 2V, the stable storage with data retention of >1E4 seconds, high endurance >1E11 cycles, CMOS compatible process, and low thermal bud get of 400oC. Amorphous InGaZnO (a-IGZO) Gate-all-around (GAA) Nanosheet FET: A-IGZO has been received much attention recently due to its low process t emperature, high electron mobility, and high uniformity, especially on the monolithic applications. Despite a-IGZO features extremely low leakage c urrent, the moderate mobility is still not compatible to the traditional gro up IV materials. GAA structure can not only increase the Ion but also decre ases the subthreshold swing (SS) and leakage current. Our team has succe ssfully developed the world first a-IGZO GAA nanosheet FET, featuring ne arly ideal SS of 61 mV/dec, extremely low Ioff of <1E-7 uA/um, high Ion/Io ff of >1.3E8、low DIBL of 44mV/V, positive threshold voltage and CMOS c ompatible process
Future Tech | Electronics ＆ OptoelectronicsThis technology uses a metalorganic chemical vapor deposition (MOCVD) system to grow a ZnGa2O4 (ZGO) with spinel epilayer on a sapphire subst rate. The MOCVD growth system of ZGO sensing epilayer is capable for m ass-produced. This ZGO epilayer can be produced into a gas sensor with a surrounding heater by a simple process. Particularly outstanding, this spin el metal oxide is currently the only metal oxide film that can sense nitric o xide. The research found that the gas sensor made of spinel thin-film only has excellent response and high selectivity for NO gas. With proper electr ode design, when in the case of NO gas, the resistance measured by this el ectrode will change. Combined with the reading signal of the circuit, the measured signal can be transmitted to the cloud by 4G network. Even in a harsh environment, the signal can be received at a safe place. On the other hand, in order to allow the gas sensor to achieve a highly sen sitive response, it is usually heated. In order to increase the temperature o f the surface of the ZGO epitaxial film to achieve the operating range of th e gas sensing element, it is also desirable to pursue the minimum work To reduce power consumption, and minimize heat dissipation, the common gas sensor adopts a suspended design, using air as its thermal insulation s hield. This technology also proposes to produce the heater on the same plane of the sensor with the insulation packaging. The heater can instantly heat th e sensor to 300°C, which contributes to improve the sensing ability of the gas sensor. Compared with the traditional gas sensor with a micro-electro mechanical suspended diaphragm, this design will have a simpler manufa cturing process and a more robust mechanical structure. Moreover, a spec ial circuit is designed to keep the resistance of the heater at a constant vol tage for maitaining heater at a constant temperature. The gas sensor can measure as low as the ppb level, and has a very high gas selectivity.
Future Tech | Electronics ＆ OptoelectronicsThe proposed technology includes 1) EHC-Frank coding to reduce interfer ence in a multiuser millimeter-wave (mmWave) radar system and 2) 3-D Pi llar-based shielding to reduce electromagnetic interference (EMI) in a mm Wave radar system-in-package (SiP). MmWave radars that can overcome severe weather conditions have been gradually used in autonomous driving. When multiple mmWave vehicle ra dars operate simultaneously, their radar signals inevitably interfere with e ach other. This interference may adversely affect the radar functions and a ccuracy, resulting in dangerous accidents. This proposed technology 1) us es the polyphase Frank code featuring high auto-correlation and low cros s-correlation and 2) reduces the cross-correlation through the Extended H yperbolic Congruential (EHC) code with one-coincidence feature to constr uct EHC-Frank codes as radar signals with high peak-to-sidelobe (PSLR) ra tio. Therefore, a vehicle radar assigned with its own EHC-Frank code can si gnificantly suppress the signals transmitted by other vehicle radars after p erforming cross-correlation, effectively reducing the interference. Due to the short-wavelength nature of mmWave frequency, mmWave acti ve and passive components, such as radar transceivers and antennas, can be integrated into a SiP through contemporary packaging technology. It c an be envisioned that EMI among the components will affect the overall s ystem performance. The proposed technology uses commercially availabl e packaging technology, such as fan-out wafer-level packaging (FOWLP) o r wire bonding, to create 3-D pillars that shield the components from EMI. No additional process steps are required. Moreover, building a row of pilla rs instead of a wall features better process uniformity and cost-effectivene ss. The above two techniques address reducing interference at the macroscal e and microscale, respectively. They can be used in parallel without conflic t to achieve a two-fold interference reduction for mmWav
Future Tech | Electronics ＆ OptoelectronicsSilicon photonics (SiPh) is an important technology in the fields of semico nductor and optoelectronics. By manufacturing SiPh chips in modern CM OS foundries, the powerful, cost-effective, and functional SiPh chips could have a wide range of applications including optical communications, bio- medical detection, and quantum-computing. However, the current bottle neck of SiPh is the lack of efficient on-chip lasers due to the indirect-band gap nature of group-IV semiconductors, limiting the further development of SiPh. Thus, it is extremely to break the fundamental limitation to create on-chip SiPh lasers. Here we demonstrate CMOS-compatible, monolithically-integrated group -IV lasers on silicon as the important on-chip lasers for silicon photonics. Using low-temperature growth technique and Ge buffer layer technique, we successfully grew high-Sn-contnet GeSn layers with a direct bandgap on silicon substrates. By processing the grown sample into laser cavities, we achieved lasing action under optical pumping. The threshold of our Ge Sn lasers is relative lower compared to the results from other group in the world, and is comparable with III-V lasers. With the CMOS-compatibility, t his technology could be used as the on-chip laser light sources for SiPh, e nabling stronger and functional SiPh chips for a wide range of application s.
Future Tech | Electronics ＆ OptoelectronicsAs phones, computers, and other electronics get smaller, the built-in optics are difficult to shrink because high-spec microscopic lenses are hard tomake with traditional glass-cutting or plastic-molding techniques. Moreover, it often requires stacking multiple traditional lenses to properly focus light. A metalens is composed of millions or even tens of millions of nanopillar arrays which are etched into a thin dielectric layer with a thickness less than one-fiftieth of the diameter of a human hair. These nanopillars canarbitrarily control the physical properties of light such as amplitude, phase, absorption, and reflection, which cannot be achieved by traditional refractive lenses. Because the metalens is so thin, multiple metalenses can bestacked together without a significant increase in size, making miniaturized optical systems possible. In addition to reducing size, metalenses couldultimately reduce the cost of optical components in electronic products, because metalenses can be fabricated using materials, processes, and equipment in today’s semiconductor industry, allowing the integration of optical and electronic components into tiny CMOS IC chips. However, making metalenses is still very costly at present, because it is difficult to precisely manufacture tens of millions of nanometer-scale elements on millimeter-scale IC chips, thus limiting the application and deployment of metalenses and metasurfaces.This work presents large-area near-infrared and visible metalenses and metasurface holograms produced with CMOS-compatible processes. Through low-cost photolithography and resolution enhancement technology, we can precisely control the sizes and shapes of nanopillars in the metalensto achieve diffraction-limited focusing with high efficiency. The present work will enable the integration of metalens and metasurfaces into CMOS image, distance, and depth sensors, allowing versatile optoelectronic components and systems in a miniature form.
Future Tech | Electronics ＆ Optoelectronics/Information ＆ Communications/Machinery ＆ SystemComing soon!
