CFETs and beyond
Technology Introduction:
Transistor stacking is a key approach for extending advanced technology nodes. This technology demonstrates monolithic split-gate CFETs and 3-tier transistor stacking for design flexibility and area scaling. By enabling independent gate control and 3-tier transistor stacking, it improves circuit flexibility, supports threshold-voltage tuning, and realizes half-SRAM and tri-state inverter circuits with potential for advanced logic transistors.
Industrial Applications:
This technology improves PPA efficiency and extends Moore＇s Law through monolithic transistor stacking. By using split-gate CFETs and 3-tier transistor stacking, it reduces cost, enhances design flexibility, enables threshold-voltage tuning, and realizes advanced logic devices with higher density, lower power consumption, and smaller area.
National Taiwan University
At present, the University consists of 16 colleges, 58 departments, 146 graduate institutes, as well as 34 Master's and PhD degree programs. NTU's programs cover a wide array of disciplines across science, arts, and the humanities, with up to 8,000 courses made available for selection each semester.
Contact Information
Name：Chee Wee Liu
Tel：02-3366-3700 #515
Address：No. 1, Sec. 4, Roosevelt Rd., Taipei 10617, Taiwan (R.O.C.)
