A power-saving memory-in-pixel (MIP) display technology was proposed, in which an innovative CBRAM memory was embedded in a display pixel to provide the image signal to the pixel, especially in a static display period, instead of repeatedly feeding it from the peripheral drivers. In addition to the power-saving, the MIP integrated with the TFT array can increase the pixel aperture ratio compared with SRAM-embedded architecture, and decrease the layout area of peripheral drivers. Furthermore, the high-conductivity copper wiring as electrodes and interconnects was integrated into the TFT backplane array, which can enhance the speed of signal transmission and reduce the image delay, beneficial for high-resolution VR/AR device applications.